1. Field of the Invention
The present invention relates to a clock generation circuit. More particularly, the present invention relates to a clock generation circuit and a controlling method thereof, the clock generation circuit performing frequency modulation for spread spectrum by accurately controlling the phase difference between a reference clock signal and an output clock signal.
2. Description of Related Art
In recent years, spread spectrum clock generators (abbreviated as SSCG) capable of reducing EMI (Electromagnetic Interference) noise have been receiving attention. SSCGs have a PLL circuit and perform frequency modulation while locking the frequency of an output clock signal to a reference clock, thereby spreading the frequency spectrum of the output clock signal. Since use of an SSCG enables efficient EMI noise reduction, there have been increasing demands for adapting of an SSCG to systems which heretofore have had difficulties in use of an SSCG.
In Japanese unexamined patent publication No. 2005-020083 shown in FIG. 8, a conventional spread spectrum clock generation circuit equipped with a PLL (Phase Locked Loop) circuit 102 is disclosed. As shown in FIG. 8, the PLL circuit 102 includes (i) a DLL circuit 108 for generating a plurality of delay clock signals having different phases by delaying an oscillation clock signal CLKO100 (hereinafter referred to as “output clock signal”) and (ii) a selector 109 for selecting one of the plurality of delay clock signals to output a selected clock signal CLKS100. In the selector 109, frequency modulation for spread spectrum is performed by switching the delay clock signals. The clock signal modulated by the selector 109 is divided in a feedback divider circuit 110 so that a comparison clock signal CLKC100 is generated.
The related art techniques are disclosed in Japanese unexamined patent publications Nos. 2005-4451, H7-202652 and H7-235862.